1. Field of the Invention
The invention relates to a pixel array and more particularly to a pixel array with favorable display quality.
2. Description of Related Art
With the progressing development of liquid crystal displays (LCDs) for large size display, wide-viewing angle of LCD panels also needs to be improved continuously to overcome the viewing-angle of large size displays. Here, multi-domain vertical alignment (MVA) LCD panels and polymer stabilized alignment (PSA) LCD panels are conventional wide viewing-angle technologies. To improve color washout in these LCD panels, advanced-MVA LCD panels have been provided. In the advanced-MVA LCD panels, each of the sub-pixel regions is divided into a main display region and a sub-display region. Through suitable circuit design and driving method, driving voltages of the main display region and the sub-display region in the same pixel are different so as to improve color washout. In conventional technology, the design concept of the sub-pixel regions having a main display region and a sub-display region has been applied in PSA LCD panels.
FIG. 1 is an equivalent circuit diagram of a pixel array. FIG. 2 illustrates a schematic diagram of a single sub-pixel in FIG. 1. Referring to FIGS. 1 and 2, a pixel array 100 includes a plurality of sub-pixels P1 arranged in an array. Each of the sub-pixels P1 includes a first thin film transistor (TFT) TFT 1, a second thin film transistor TFT2, a third thin film transistor TFT3, a first pixel electrode ITO1 electrically connected to the first thin film transistor TFT1, and a second pixel electrode ITO2 electrically connected to the second thin film transistor TFT2. The first pixel electrode ITO1 is coupled to a common line COM1 to generate a first storage capacitance Cs1. The first pixel electrode ITO1 is coupled to a common electrode (not shown) on an opposite substrate (i.e. a color filter substrate) to generate a first liquid crystal capacitance CLC1. Similarly, the second pixel electrode ITO2 is coupled to a common line COM2 to generate a second storage capacitance Cs2. The second pixel electrode ITO2 is coupled to a common electrode (not shown) on an opposite substrate (i.e. a color filter substrate) to generate a second liquid crystal capacitance CLC2.
As shown in FIGS. 1 and 2, in the sub-pixel P1 electrically connected to a scan line SL(n−1), a gate G1 in the first thin film transistor TFT1 and a gate G2 in the second thin film transistor TFT2 are electrically connected to the scan line SL(n−1) respectively. Moreover, a gate G3 in the third thin film transistor TFT3 is electrically connected to a scan line SL(n) subsequently. In addition, a source S3 of the third thin film transistor TFT3 is electrically connected to the second pixel electrode ITO2, a drain D3 of the third thin film transistor TFT3 is coupled to the first pixel electrode ITO1 to generate a first capacitance Ccs-a, and a drain D3 of the third thin film transistor TFT3 is coupled to the common line COM1 underneath the first pixel electrode ITO1 to generate a second capacitance Ccs-b. When a high voltage (Vgh) is applied to the scan line SL(n−1), an image data is recorded into the sub-pixel connected to the scan line SL(n−1) through data lines DL(m−1) and DL(m). At this time, the first pixel electrode ITO1 and the second pixel electrode ITO2 have the same voltage. Next, when a high voltage is applied to the scan line SL(n), coupling effect of the first capacitance Ccs-a and the second capacitance Ccs-b makes a voltage of the first pixel electrode ITO1 and a voltage of the second pixel electrode ITO2 to be different.
Since a drain D2 of the second thin film transistor TFT2 is overlapped with the first pixel electrode ITO1 and electrically connected with the second pixel electrode ITO2, a parasitic capacitance Cx1 is generated between the drain D2 of the second thin film transistor TFT2 and the first pixel electrode ITO1. In addition, as the drain D3 of the third thin film transistor TFT3 is overlapped with the second pixel electrode ITO2, a parasitic capacitance Cx2 is generated between the drain D3 of the third thin film transistor TFT3 and the second pixel electrode ITO2. The parasitic capacitance Cx1, Cx2 decrease the voltage difference range of the first pixel electrode ITO1 and the second pixel electrode ITO2, so that the color washout can not be improved effectively. Accordingly, it is necessary to prevent the parasitic capacitance Cx1, Cx2 in the sub-pixel P1 from affecting display quality.